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Integrated Circuit Systems, Inc.
ICS9250-29
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: Solano type chipset. Output Features: * 2 CPU (2.5V) (up to 133MHz achievable through I2C) * 13 SDRAM (3.3V) (up to 133MHz achievable through I2C) * 5 PCI (3.3 V) @33.3MHz * 1 IOAPIC (2.5V) @ 33.3 MHz * 3 Hublink clocks (3.3 V) @ 66.6 MHz * 2 (3.3V) @ 48 MHz (Non spread spectrum) * 1 REF (3.3V) @ 14.318 MHz Features: * Supports spread spectrum modulation, 0 to -0.5% down spread. * I2C support for power management * Efficient power management scheme through PD# * Uses external 14.138 MHz crystal * Alternate frequency selections available through I2C control.
IOAPIC VDDL GNDL *FS1/REF VDDR X1 X2 GNDR VDD3 3V66-0 3V66-1 3V66-2 GND3 PCICLK0 PCICLK1 PCICLK2 VDD2 GND2 PCICLK3 PCICLK4 FS0 GNDA VDDA SCLK SDATA GNDF VDDF 48MHz_0
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GNDL VDDL CPUCLK0 CPUCLK1 GND1 SDRAM0 SDRAM1 VDD1 GND1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDD1 GND1 SDRAM6 SDRAM7 SDRAM8 SDRAM9 VDD1 GND1 SDRAM10 SDRAM11 VDD1 GND1 SDRAM12 TRISTATE#/PD#** 48MHz_1
56-Pin 300mil SSOP
* This input has a 50K9 pull-down to GND. ** This input has a 50K9pull-up to VDD
Block Diagram
Functionality
Tristate# FS0 0 1 0 1 0 1 FS1 X X 0 0 1 1 CPU MHz Tristate Test 66MHz 100MHz 133MHz 133MHz SDRAM MHz Tristate Test 100MHz 100MHz 133MHz 100MHz
X1 X2
XTAL OSC PLL1 Spread Spectrum /2 /3
REF
VDDL
2
CPU66/100/133 [1:0] 3V66 [2:0] SDRAM [12:0] PCICLK [4:0] IOAPIC VDDL
0 0 1 1 1 1
FS(1:0) PD# TRISTATE# SDATA SCLK
Control Logic Config Reg /2 /2
3 13 5
Power Groups
VDDA, GNDA = CPU, PLL (analog) VDDF, GNDF = Fixed PLL, 48M (analog/digital) VDDR, GNDR = REF, X1, X2 (analog/digital) VDD3, GND3 = 3V66 (digital) VDD2, GND2 = PCI (digital) VDD1, GND1 = SDRAM (digital) VDDL, GNDL = IOAPIC, CPU (digital)
PLL2
2
48MHz [1:0]
9250-29 Rev A 02/01/01 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9250-29
ICS9250-29
General Description
The ICS9250-29 is a single chip clock solution for Solano type chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-29 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER 1 2, 55 3, 56 4 5, 9, 17, 23, 27, 33, 37, 43, 49 6 7 P I N NA M E IOAPIC VDDL GNDL FS1 REF VDDx X1 X2 TYPE OUT PWR PWR IN OUT PWR IN OUT PWR OUT IN OUT IN DESCRIPTION 2.5V clock output running at 33.3MHz. 2.5V power supply for CPU & IOAPIC Ground for 2.5V power supply for CPU & IOAPIC Function Select pin. Determines CPU frequency, all output functionality 3.3V, 14.318MHz reference clock output. 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B Function Select pin. Determines CPU frequency, all output functionality. 3.3V PCI clock outputs At power up the TRISTATE#/PD# pin defaults to the TRISTATE# input function to enable the TRISTATE# and TEST modes. (see Shared Pin Operation for full description). Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock input of I2C input Data input for I2C serial input. 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s . 3.3V output running 100MHz and 133MHz. All SDRAM outputs can be turned off through I2C 2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending on FS pins.
8, 13, 18, 22, 26, GNDx 32, 36, 42, 48, 52 12, 11, 10 21 3V66 (2:0) FS0
20, 19, 16, 15, 14 PCICLK (4:0) TRISTATE# 30 PD# 24 25 29, 28 SCLK SDATA 48MHz (1:0)
IN IN IN OUT OUT OUT
31, 34, 35, 38, SDRAM 39, 40, 41, 44, [12:0] 45, 46, 47, 50, 51 53, 54 CPUCLK (1:0)
2
ICS9250-29
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
Maximum Allowed Current
Solano Condition Powerdown Mode (PWRDWN# = 0) Full Active 66MHz FS(1:0) = 00 Full Active 100MHz FS(1:0) = 01 Full Active 133MHz FS(1:0) = 11 Full Active 133MHz FS(1:0) = 10 Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 2.625V All static inputs = Vddq3 or GND 2mA 35mA 50mA 60mA 60mA Max 3.3V supply consumption Max discrete cap loads, Vddq3 = 3.465V All static inputs = Vddq3 or GND 2mA 440mA 430mA 440mA 500mA
Clock Enable Configuration
PD# 0 1 CPUCLK LOW ON SDRAM LOW ON IOAPIC LOW ON 3V66 LOW ON PCICLK LOW ON REF, 48MHz LOW ON Osc OFF ON VCOs OFF ON
3
ICS9250-29
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
* * * * * * * * * * Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit ICS (Slave/Receiver)
ACK
Note: This clock does not support Read Back. Doing a read back will lock up the PIIX-4 system.
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C (SMB) component. It is only a "write" mode SMB device, no readback on this part. Read-Back will lock up the PIIX-4 due to the Byte count of 00H. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
4
ICS9250-29
Truth Table
Tristate 0 0 1 1 1 1 FS0 0 1 0 1 0 1 FS1 X X 0 0 1 1 CPU Tristate TCLK/2 66.6 MHz 100 MHz 133 MHz 133 MHz SDRAM Tristate TCLK/2 100 MHz 100 MHz 133 MHz 100 MHz 3V66 Tristate TCLK/3 66.6 MHz 66.6 MHz 66.6 MHz 66.6 MHz PCI Tristate TCLK/6 33.3 MHz 33.3 MHz 33.3 MHz 33.3 MHz 48MHz Tristate TCLK/2 48 MHz 48 MHz 48 MHz 48 MHz REF Tristate TCLK 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz IOAPIC Tristate TCLK/6 33.3 MHz 33.3 MHz 33.3 MHz 33.3 MHz
Byte 0: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 29 28 -
Name (Reserved ID) (Reserved ID) (Reserved ID) (Reserved ID) Spread Spectrum 48MHz_1 48MHz_0 (Reserved ID)
PWD 0 0 0 1 0 1 1 0
Description (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (1=On / 0=Off ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive )
Note: Reserved ID bits must be written with "0"
Byte 1: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 40 41 44 45 46 47 50 51
Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
PWD 1 1 1 1 1 1 1 1
Description (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive )
5
ICS9250-29
Byte 2: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 12 31 34 35 38 39 15 -
Name 3V66_2 (AGP) SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8 PCICLK1 Undefined bit
PWD 1 1 1 1 1 1 1 0
Description (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive )
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 3. Undefined bits can be written with either "1" or "0" Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ICS Reserved bit (Note 2) ICS Reserved bit (Note 2) ICS Reserved bit (Note 2) ICS Reserved bit (Note 2)
Description
PWD 0 0 0 0 0 1 1
5% overclock mode (1 = 5% / 0= normal ) Undefined bit (note 3) Tristate#/PWRDN# ( 1 = PWRDN# / 0 = Tristate# ) see pin description Bit 0 0 0 0 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPUCLK SDRAM MHz MHz 66.66 100.0 133.32 133.32 66.66 100.0 133.32 133.32 100.0 100.0 133.32 100.0 100.0 100.0 133.32 133.32 3V66 MHz 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 PCICLK IOAPIC MHz MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33
Bit 0
0 1 1 1 1
0 Note 1
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS1 for the appropriate CPU speed, always with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI and IOAPIC clocks will be glitch free during this transition, and only SDRAM will change. Note 2: Must be written with "0" Note 3: Undefined bits can be written with either "1" or "0"
6
ICS9250-29
Byte 4: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 20 19 16
Name (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) PCICLK4 PCICLK3 PCICLK2
PWD 0 0 0 0 0 1 1 1
Description (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive )
Byte 5: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
Name (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
PWD 0 0 0 0 0 0 0 0
Description (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive ) (Active / Inactive )
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
7
ICS9250-29
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Timing Relationship Table1
Group CPU 66MHz SDRAM 100MHz Offset CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to IOAPIC USB & DOT -2.5ns 7.5ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1ns N/A CPU 100MHz SDRAM 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1ns N/A CPU 133MHz SDRAM 100MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1ns N/A CPU 133MHz SDRAM 133MHz Offset 3.75ns 0.0ns -3.75ns 1.5 -3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1ns N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance1 Input Capacitance1 Transition Time Settling Time
1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi Lpin CIN Cout CINX Ttrans Ts TSTAB t PZH,t PZH t PLZ,t PZH
CONDITIONS
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs)
MIN 2 VSS-0.3 -5 -5 -200
TYP
MAX UNITS VDD+0.3 V 0.8 V 5 A A A 100 600 mA A MHz 7 5 6 22.5 3 3 3 10 10 nH pF pF pF ms ms ms ms ms
14.318
13.5
Clk Stabilization 1 Delay 1
1
1 1
Guarenteed by design, not 100% tested in production.
8
ICS9250-29
Electrical Characteristics - CPU
TA = 0 - 70C, VDD=3,3V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP2B1 RDSN2B1 VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1 dt2B1 tsk2B1 tjcyc-cyc1 VO = VDD*(0.5)
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 13.5 13.5 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 45 45 0.4 -27 30 V V mA mA ns ns % ps ps
1.10 1.26 53.6
1.6 1.6 55 175 250
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%;CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1 1 1 1 1
CONDITIONS VO = VDD*(0.5)
MIN 12
TYP
MAX UNITS 55 55 0.4 -33 38 V V mA mA ns ns % ps ps
VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4V 30 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 0.5 0.5 45 1.46 1.47 50.2
2 2 55 175 500
dt1
tsk1
tjcyc-cyc1
Guarenteed by design, not 100% tested in production.
9
ICS9250-29
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP4B1 RDSN4B1 VOH4B VOL4B IOH4B IOL4B tr4B1 tf4B1 dt4B1 tjcyc-cyc1 VO = VDD*(0.5)
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ min = 1.0 V, VOH@ MAX = 2.375 V VOL@ MIN = 1.2 V, VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 9 9 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 30 30 0.4 -27 30 V V mA mA ns ns % ps
1.09 1.22 50.2
1.6 1.6 55 500
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%, CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP3 RDSN3 VOH3 VOL3 IOH3 IOL3 tr31 tf3
1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, VOH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V
MIN 10 10 2.4 -54 49 0.4 0.4 45
TYP
MAX UNITS 24 24 0.4 -46 53 V V mA mA ns ns % ps ps
1.19 1.43 54.9
1.6 1.6 55 250 250
dt31
VT = 1.5 V tsk31 1 tj cyc-cyc VT = 1.5 V
Guarenteed by design, not 100% tested in production.
10
ICS9250-29
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1 1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 12 2.4 -33 30 0.5 0.5 45
TYP
MAX UNITS 55 55 0.4 -33 38 V V mA mA ns ns % ps ps
1.43 1.63 51.9
2 2 55 500 500
dt1
tsk1
tjcyc-cyc1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%, CL = 10 -20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP5 RDSN5 VOH5 VOL5 IOH5 IOL5 tr51 tf5
1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN=1 V, VOH@MAX= 3.135 V VOL@MIN=1.95 V, VOL@MIN=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V; Fixed Clocks VT = 1.5 V; Ref Clocks
MIN 20 20 2.4 -29 29 1 1 45
TYP
MAX UNITS 60 60 0.4 -23 27 V V mA mA ns ns % ps ps
1.53 1.76 53.6
4 4 55 500 1000
dt5
tjcyc-cyc1 tjcyc-cyc1
Guarenteed by design, not 100% tested in production.
11
ICS9250-29
Electrical Characteristics - 48MHz_1
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 15 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP3 RDSN3 VOH3 VOL3 IOH3 IOL3 tr31 tf3
1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, VOH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V
MIN 10 10 2.4 -33 30 0.5 0.5 45
TYP
MAX UNITS 24 24 0.4 -33 38 V V mA mA ns ns % ps
0.81 0.95 53.1
2.0 2.0 55 500
dt31 VT = 1.5 V tjcyc-cyc1 VT = 1.5 V
Guarenteed by design, not 100% tested in production.
12
ICS9250-29
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz CPU 100MHz CPU 133MHz
SDRAM 100MHz SDRAM 133MHz
3.3V 66MHz PCI 33MHz IOAPIC 33MHz REF 14.318MHz USB 48MHz
Group Offset Waveforms
13
ICS9250-29
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9250-29 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
TRISTATE#/PD# pin description:
The TRISTATE#/PD# pin provides the capability of invoking Tristate mode during board level testing. At power up the TRISTATE#/PD# pin defaults to the TRISTATE# input function to enable the TRESTATE# and TEST modes. Approximately 1.5ms to 3ms after power on, the TRISTATE#/ PD# changes to the PD# input function and the TRISTATE# functionality is disabled (if TRISTATE# is not active).
14
ICS9250-29
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 56
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 18.288 MAX 18.542 MIN .720
D (inch) MAX .730
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9250yF-29-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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Price & Availability of ICS9250-29

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